1. Field of the Invention
The present invention is related to a digital phase-locked loop (referred to as DPLL, hereinafter) circuit used, for example in a modem (modulator-demodulator) of a portable radio telephone set.
2. Description of the Related Art
A conventional circuit will be described hereinbelow by taking the case of a modem incorporated in a portable radio telephone set.
In general, the DPLL circuit of this sort is provided with a function for generating an internal clock used for other circuits of the telephone set (referred to as internal or output clock, hereinafter) and a function for synchronizing the phase of the generated internal clock (i.e., an output clock) with that of a clock component of a received signal (i.e., an input clock).
An example of the DPLL circuit of this sort will be described hereinbelow with reference to FIG. 8, by way of example. In the drawing, a received analog signal S.sub.A is converted into digital received signals S.sub.D by an analog to digital converting circuit 705, detected by a delay detecting circuit 706, and further processed by a clock extracting narrow-band circuit (referred to as TANK circuit, hereinafter) 707 to extract received clock components corresponding to a symbol rate. Further, received clock component extracting signals TNK indicative of the clock components are supplied to a DPLL circuit 701.
As shown, the DPLL circuit 701 is composed of a phase comparator 702, a random walk filter 703 and a variable-frequency oscillator 704.
The phase comparator 702 inputs the received clock component extracting signals TNK and an internal clock SCK generated by the variable-frequency oscillator 704, and detects a phase difference between the two (TNK and SCK) for each cycle. The detected phase difference data for each cycle are outputted to the random walk filter 703.
The random walk filter 703 adds the inputted phase difference data for each cycle in sequence and accumulates the added data. Further, when the absolute value of the accumulated data exceeds a predetermined threshold value, the random walk filter 703 outputs a frequency change signal.
In response to this frequency change signal, the variable-frequency oscillator 704 changes the frequency of the internal clock for a predetermined time period according to the inputted frequency change signal. Owing to a change of the frequency of the internal clock SCK, the phase of the internal clock SCK is shifted in a direction that the phase of the internal clock SCK matches the phase of the received clock component extracting signal TNK.
In the above-mentioned conventional DPLL circuit 701, the threshold value in the random walk filter 703 and the phase shift amount (for each detection) of the internal clock in the variable-frequency oscillator 704 are both determined to be constant at all times.
However, the optimum values of the threshold voltage and the phase shift amount vary according to the phase difference between the internal clock and the received clock. In other words, when the phase difference is large, it is preferable to set the threshold value to a relatively low value and the phase shift amount to a relatively large value, in order to reduce the phase difference between the both TNK and SCK to zero during a relatively short time period. On the other hand, when the phase difference is small, it is preferable to set the threshold value to a relatively high value and the phase shift amount to a relatively small value, in order to match the both phases with respect to each other with a high precision.
Here, in general, the phase difference increases at the initial synchronous operation, and decreases in the continuous reception operation. In the conventional DPLL circuit 701, however, the threshold value and the phase shift amount are determined according to the magnitude of the phase difference detected in the continuous reception operation.
Therefore, in the conventional DPLL circuit, although a high precise phase matching operation can be realized in the continuous reception operation, it is difficult to realize the phase matching in a short time period in the initial synchronous operation, and thus it has been difficult to realize a high performance DPLL.
A symbol timing reproducing circuit is disclosed in Japanese Patent Laid-open (Kokai) No. 4-40029 (1992). In this circuit, the numbers of the overflows and/or underflows due to an initially determined inertia are accumulated, and the mode is updated when the accumulated value exceeds a threshold value m so that the inertia can be increased stepwise.
In this prior art circuit, however, since the inertia is controlled only by the phase difference information, there exists a problem in that in case the phase difference is reduced down to zero accidentally at the start of phase matching operation, the operation proceeds under a small inertial, so that it is impossible to decide the optimum inertial accurately according to the operating conditions of the DPLL circuit.